1. Field of the Invention
The present invention relates to a semiconductor device on which is mounted a semiconductor element, for transferring a high-speed signal, and a printed circuit board therefor, and particularly to the wiring on a resin substrate (an interposer) of a semiconductor package, such as a BGA or a CSP.
2. Description of the Related Art
Recent electronic apparatuses, such as personal computers, include an I/F such as a USB or an IEEE 1394. The I/F transmits a very high-speed signal having a pulse width that corresponds, after being converted, to a frequency of several hundreds of megahertz. The speed of a signal has been increased even more, and there is a demand for the transmission of a signal that corresponds to a frequency of one gigahertz.
Further, multifunctional ICs and IC modules have been developed that are like system LSI chips, and these ICs are mounted in multi-terminal packages, such as BGAs or CSPs. That is, an IC having a high-speed signal transmission I/F tends to be mounted in a multi-terminal semiconductor package, such as a BGA or a CSP. Generally, in a semiconductor package, a semiconductor element is connected by wire bonding to electrode pads on a resin substrate (an interposer) whereon the semiconductor element is mounted. These electrode pads are connected to the interposer by signal lines extended radially on the interposer. The electrode pads are also connected through vias to ball pads that are provided on the reverse face of the interposer to attach the semiconductor package to a motherboard.
Gold plating is required for the electrode pads on the interposer. In order to perform the gold plating for the electrode pads, the electrode pads must be rendered conductive from the outer edge of the interposer. Therefore, in addition to wiring connected to the mounted semiconductor element, other wiring is extended from the outer edge of the interposer to the individual electrode pads. Wiring extended from an individual electrode pad to the outer edge of the interposer is called a “plating stub”. A plating stub has an open end at the outer edge of the interposer, along the transmission line, and the length of the stub is about 1 to 4 mm for a BGA package, of a peripheral type, with 1 mm pitches and four rows.
FIG. 8 is a partial, opened-up view of a semiconductor package employing a conventional BGA, for which, to simplify the explanation, the interior is shown. An interposer substrate 101 in FIG. 8 has a two-layer structure; however, a multi-layer structure of three or more layers may be used. A semiconductor element 110 mounted on the interposer substrate 101 is connected to electrode terminals 103a and 103b on the interposer substrate 101 by wires 102, and the electrode terminals 103a and 103b are connected to electrode pads 105a and 105b by signal lines 104a and 104b. Plating stubs 106a and 106b are extended from the electrode pads 105a and 105b to the outer edge of the interposer substrate 101. The electrode pads 105a and 105b are connected by vias 107a and 107b, which are formed in the interposer substrate 101, to ball pads 108a and 108b on the reverse surface of the interposer substrate 101. The ball pads 108a and 108b are connected by solder balls 109a and 109b to a motherboard (not shown).
Generally, when a period during which a signal reciprocates along a signal line in the open state is longer than the rise time for the signal, a reflected waveform occurs in the signal waveform and causes waveform distortion. For a signal for which the waveform is trapezoidal, the rise time for the signal is generally equal to about 5% of the cycle. Therefore, for a conventionally employed signal having a frequency of 1 GHz, the cycle is about 1.0 nsec and the rise time, which is 5% of the cycle, is 0.050 nsec. Through a calculation performed by employing a signal transfer rate of 6 nsec/m for a common glass epoxy substrate, the equivalent length obtained, for both directions is 8.30 mm, and the wiring length obtained that corresponds to one direction is 4.15 mm. That is, in the open state, a plating stub of about 1 to 4 mm in length does not greatly affect the quality of the waveform.
Furthermore, according to the description in Japanese Patent Laid-Open Publication 2001-110927, ten times the high frequency component of a signal used for a semiconductor element is taken into account, and in the open state, the length of a plating stub is designated as being less than ¼ of the upper limit wavelength in a frequency band (smaller than 3.5 mm for a case wherein the frequency is 1 GHz).
However, the frequency of a signal used for the semiconductor element has been repeatedly increased, and a signal having a frequency even greater than 2 GHz is now employed. For a signal having a frequency of 2 GHz, the cycle is 0.5 nsec and the rise time, which is 5% of the cycle, is 0.025 nsec. Through calculations performed using the signal transfer rate of 6 nsec/m, the equivalent length in both directions is 4.15 mm, and the wiring length corresponding to one direction is 2.08 mm. That is, in the open state, a plating stub of about 2 mm or longer would greatly affect the waveform of a signal to be transmitted.
As is apparent from the conventional semiconductor package shown in FIG. 8, the plating stub 106a extending from the outer electrode pad 105a is short, and the plating stub 106 extending from the inner electrode pad 105b is long. Therefore, in order for the length of the plating stub, for the wiring along which a high-frequency signal is transmitted, to be less than ¼ of the upper limit wavelength for the frequency band, as described in Japanese Patent Laid-Open Publication 2001-110927, the outer electrode pad 105a must be employed as the electrode pad to be connected to the wiring described above.
When there is such a restriction, much of the flexibility of the design of the interposer, and of the motherboard, is lost, and not only are design costs increased, but also, the preparation of a viable design therefor would be impossible.
Further, since recently a differential transmission method is frequently adopted for high-speed signals, differential pair of signal lines for which impedance matching is required must be provided on the interposer. In order to acquire impedance matching for the differential pair of signal lines, a predetermined clearance must be maintained between two signal lines of a differential pair of signal lines. However, it is very difficult, while maintaining this clearance, for the differential pair of signal lines to be passed through a number of electrode pads and connected to the electrode pads nearest the outer edge of the interposer substrate. Therefore, in order to match the differential impedances of the differential pair of signal lines, these wires must be connected to the innermost electrode pads on the interposer, so that the lengths of the plating stubs are increased, and the distortion of waveforms for signals to be transmitted can not be avoided.